1. Field of the Invention
The present invention relates generally to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a twin-well in which a well potential is varied in accordance with operations, and a memory element formed in the twin-well, and also having an N-well and a P-well that are separated away from the twin-well.
2. Description of the Related Art
A memory cell of a nonvolatile semiconductor memory device, such as an EEPROM, normally has a MISFET structure wherein a charge accumulation layer and a control gate are stacked on a semiconductor substrate. The memory cell stores data in a nonvolatile state by a difference between a threshold in a state in which charge, e.g. electrons, is injected in the charge accumulation layer, and a threshold in a state in which the electrons are discharged. Of EEPROMs, a NAND-type EEPROM, which has a so-called NAND cell unit with a plurality of series-connected memory cells, can realize a higher integration density than a NOR-type EEPROM, since the number of select transistors in the NAND-type EEPROM can be made less than that in the NOR-type EEPROM.
In the NAND-type EEPROM, the injection and release of charge are effected by causing a tunneling current to flow through a tunneling insulation film that is formed between the charge accumulation layer and the substrate channel. In the NOR-type EEPROM, too, the tunnel current is used to erase data in order to reduce a short-channel effect at a time of data erasure.
The erasure of data is executed for a plurality of memory cells at a time, for example, in order to increase the number of memory cells for data erasure per unit time. To achieve this, a positive voltage of, e.g. 15V or more is applied to the cell well where the memory cell is formed, thereby drawing electrons out of the charge accumulation layer into the substrate. On the other hand, at a time of data write/read, the voltage at the cell well is kept at 0V, and the voltage that is applied to the source/drain of the memory cell is lowered. Thereby, the power for charging/discharging the cell well is decreased, and the operation speed is increased.
The EEPROM has a so-called twin-well structure wherein a P-well is surrounded by an N-well, and the P-well is electrically isolated from the semi-conductor substrate. Thereby, the cell well voltage can be varied in accordance with operations (e.g. U.S. Pat. No. 6,411,548).
FIG. 1 is a cross-sectional view showing a prior-art EEPROM having a twin-well.
As is shown in FIG. 1, a P-type cell well (cell P-well) 10 is formed in a P-type semiconductor substrate (P-sub) 1. An N-type well (N-well) 7 is formed on side surfaces of the P-type cell well 10. An N-type well 9 (deep-N-well) 9 is formed under the P-type cell well 10. An N-type well 8 is formed in contact with side surfaces of the N-type well 9. An upper part of the N-type well 8 is in contact with the lower part of the N-type well 7.
The P-type cell well 10, as described above, is surrounded by the N-type wells 7, 8 and 9 and is electrically isolated from the P-type substrate 1. This is the twin-well architecture. Memory cell transistors Q5-1 and Q5-2 are formed in the P-type cell well 10 of the twin-well.
The P-type cell well 10 has a depth of, e.g. 0.6 μm.
The N-type well 7, 8, 9 needs to be formed deeper than the P-type well 10, and is formed in the P-type substrate 1 that has a low impurity concentration, for instance, an impurity concentration lower than 1015 cm−3. In addition, in order to keep voltage constant, the N-type well 7, 8, 9 is formed with a peak concentration of, e.g. 1016 cm−3 or more. Consequently, the N-type well 7, 8, 9 spreads within the P-type substrate 1 with a depth of, e.g. 2 μm.
The EEPROM includes not only the memory cell transistors Q5-1 and Q5-2, but also logic peripheral circuits such as a control circuit for controlling the transistors Q5-1 and Q5-2 and a voltage control circuit for controlling the voltage of the P-type cell well 10. The EEPROM further includes a high voltage generating circuit for generating a high positive voltage for use in erasure, and a device and a circuit that use high voltage.
In order to form these circuits, P-type wells 2, 3 and 4 and N-type wells 5 and 6 are formed apart from the twin-well within the P-type semiconductor substrate 1.
The P-type well 2, 3, 4 has a depth of, e.g. about 1 μm.
The N-type well 5, 6 has the same depth as the N-type well 7, 8, 9, which is, e.g. 2 μm or more.
The logic peripheral circuit is composed of a CMOS circuit. A P-channel transistor (MOSFET) Q1 of the CMOS circuit is formed in the N-type well 5, 6, and an N-channel transistor (MOSFET) Q3 of the CMOS circuit is formed in the P-type well 3.
The high voltage generating circuit or the device or circuit that uses high voltage is composed of a high-withstand-voltage transistor having more excellent electrical withstand voltage characteristics than the peripheral circuit transistor that forms the logic peripheral circuit. A P-channel high-withstand-voltage transistor Q2 is formed in the N-type well 5, 6, and an N-channel high-withstand-voltage transistor Q4 is formed in the P-type substrate 1.
The P-type well 2 is a well for isolating the N-type well 5, 6, in which the high voltage generating circuit is formed, from the N-type well 5, 6, in which the logic peripheral circuit is formed. Similarly, the P-type well 4 is a well for isolating the twin-well from the high withstand voltage transistor Q4.
FIG. 2 to FIG. 4 are cross-sectional views illustrating the method of fabricating the EEPROM shown in FIG. 1.
To start with, a sacrificial oxide film 17 is formed on the P-type semiconductor substrate 1. A photoresist film 18 is formed on the sacrificial film 17. The thickness of the photoresist film 18 is between 1.8 μm and 4 μm. Subsequently, the photoresist film 18 is exposed/developed, and openings corresponding to a formation pattern of N-type wells 5, 6, 7, 8 are formed in the photoresist film 18. Using the photoresist film 18 as a mask, impurities, such as phosphorus or arsenic, for forming the N-type wells 5, 6, 7, 8, are ion-implanted in the substrate 1.
Next, as shown in FIG. 3, the photoresist film 18 is removed, and a photoresist is coated once again on the insulation film 17, and a photoresist film 19 is formed. The thickness of the photoresist film 19 is 1.6 μm or less. The photoresist film 19 is exposed/developed, and openings corresponding to a formation pattern of P-type wells 2, 3, 4 are formed in the photoresist film 19. Using the photoresist film 19 as a mask, impurities, such as boron or indium, for forming the P-type wells 2, 3, 4, are ion-implanted in the substrate 1.
Thereafter, as shown in FIG. 4, the photoresist film 19 is removed, and a photoresist is coated once again on the insulation film 17, and a photoresist film 20 is formed. The thickness of the photoresist film 20 is between 1.8 μm and 4 μm. The photoresist film 20 is exposed/developed, and an opening corresponding to a formation pattern of a P-type well 10 is formed in the photoresist film 20. Using the photoresist film 20 as a mask, impurities, such as phosphorus or arsenic, for forming an N-type well 9, are ion-implanted in the substrate 1. Further, using the photoresist film 20 as a mask, impurities, such as boron or indium, for forming the P-type well 10, are ion-implanted in the substrate 1.
Subsequently, as shown in FIG. 1, transistors Q1 to Q4 and memory cell transistors Q5-1 and Q5-2 are formed in the P-type substrate 1, P-type well 3, N-type wells 5, 6 and P-type cell well 10, respectively.
As regards the EEPROM shown in FIG. 1, however, there are the following circumstances.
(1) The depth L1 of the N-type well 5, 6 is equal to the depth L2 of the N-type well 9. Thus, the depth L1 of the N-type well 5, 6 is typically 2 μm or more.
Since the depth L1 of the N-type well 5, 6 is very large, the width z′ of the P-type well 2 cannot be reduced to, e.g. 2 μm or less. If the width z′ of the P-type well 2 is reduced to 2 μm or less, a punch-through current would flow through the substrate 1 under the P-type well 2 between the N-type well 5, 6, in which the high voltage generating circuit is formed, and the N-type well 5, 6, in which the logic peripheral circuit is formed. This phenomenon is particularly conspicuous when a high voltage of, e.g. 10V to 15V or more, relative to the P-type substrate 1, is applied to the N-type well 5, 6 where the high voltage generating circuit is formed.
Under the above circumstances, in the EEPROM shown in FIG. 1, it is difficult to reduce the distance x between the N-type well 5, 6, where the high voltage generating circuit is formed, and the N-type well 5, 6, where the logic peripheral circuit is formed.
In the case where a high voltage of 15V or more is applied to the N-type well 5, 6 in which the high voltage generating circuit is formed, it is also difficult to reduce the distance between the N-type well 5, 6 and the P-type well 2 to, e.g. 0.5 μm or less. The reason is that since regions with high impurity concentrations of a PN junction are located close to each other, a region with a high electric field occurs, resulting in degradation in junction breakdown voltage.
(2) Since the depth L1 of the N-type well 5, 6 is very large, the width of the N-type well 5, 6 tends to increase. Similarly, the width of the N-type well 7, 8 tends to increase. The reason is that the depth of the N-type well 7, 8 is equal to the depth L2 of the N-type well 9.
This is partly because the photoresist film 18 with a very large thickness of 1.8 μm is used in the photolithography step illustrated in FIG. 2. If the thickness of the photoresist film is large, the width of the N-type well 5, 6 tends to increase due to fall-down of the photoresist or due to resolution. For example, the width of the N-type well 5, 6 tends to become greater than the width z′ of the P-type well 2 that is formed shallower than the N-type well 5, 6. Similarly, the width z of the N-type well 7, 8 tends to become greater than, e.g. the width z′ of the P-type well 2.
Furthermore, reduction in the distance x is hindered by the fact that the width of the N-type well 5, 6 tends to increase. Besides, reduction in distance y between the N-type well 7, 8 and the source/drain diffusion layer of the high-withstand-voltage transistor Q4 may possibly be hindered by the fact that the width z of the N-type well 7, 8 tends to increase.